Tamagotchis Need Not Die { Veriication of Statemate Designs

This paper presents a toolset we built for supporting veriication of Statemate 1 designs. Statemate is a widely used design tool for embedded control applications. Designs are translated into nite state machines which are optimized and then veriied by symbolic model checking. To express requirement speciications the visual formalism of symbolic timing diagrams is used. Their semantics is given by translation into temporal logic. If the model checker generates a counterexample, it is retranslated into either a symbolic timing diagram or a stimulus for the Statemate simulator.